A prior art data transmission system 100a as shown in FIG. 1 includes a transmitter 102a for transmitting data to a receiver 104a over a data bus 106a. When data DATA[0]-DATA[N] is to be transmitted from the transmitter 102a to the receiver 104a, the transmitter 102a sends, along with the data, a data valid signal DV to notify the receiver that it is transmitting new data. The receiver 104a samples the data on the data bus 106a when the DV signal is asserted by the transmitter.
The frequency determining delay between the registers of the transmitter 102a and the registers of the receiver 104a is determined by the wire delay of the DV signal plus the fan-out delay of the DV signal feeding all of the multiplexers of the receiver 104a. When the DV signal must be input to many multiplexers, and the distance between the transmitter 102a and receiver 104a is long, the DV signal loses strength during its transmission, causing an operation frequency bottleneck. Therefore, this implementation of the DV signal causes the entire chip on which the transmitter and receiver are included to run at lower frequencies than may be desirable. The same principle applies to the WAIT signal (not shown in FIG. 1), which is transmitted from the receiver 104a to the transmitter 102a in a similar fashion as the DV signal, when the receiver pauses an ongoing data transmission.
One approach to increase the frequency of the data transmission system 100a is shown in FIG. 2. As shown in FIG. 2, data transmission system 100b includes a transmitter 102b for transmitting data to a receiver 104b over a data bus 106b. Receiver 104b includes a register stage 108 for registering the data on the data bus 106b, including the DV signal and the data DATA[0]-DATA[N].
In this data transmission system 100b, the long distance delay between the transmitter and receiver is split into two delays, which allows the data transmission system 100b to operate at higher frequencies. In this system 100b, the DV signal and data are transmitted concurrently and registered in the register stage 108 and then the data is transmitted to the inputs of the multiplexers concurrently with the DV signal, which is transmitted to the control input of the multiplexers.
While this system 100b reduces the delay in transmitting the DV signal and enables the system to operate at higher frequencies, the latency of the system is increased and the gate count is increased significantly over the system 100a. 
Data transmission systems such as 100a and 100b typically include several transmitters 102 that compete with each other for the ability to transmit data to the receiver 104. The receiver must arbitrate between the transmitters to grant access to the receiver by one transmitter at a time. Typically, this involves a series of handshake signals between the transmitter and receiver. For example, in order to gain access to the receiver for a data transmission, the transmitter requests the data transfer by asserting a request signal. When the receiver grants access to a particular transmitter, it asserts a grant signal to the particular transmitter. The transmitter then begins the transmission of the data and the data valid signal DV. The receiver then receives the data, but can pause the transmission by asserting the WAIT signal for the particular transmitter. Accordingly, the number of handshake signals required in this data transmission is four.
The number of handshake signals is directly proportional to the design complexity and verification time of the data transmission system. Therefore, fewer handshake signals will result in a less complex system that is simpler to design and which results in shorter verification times.
In the event that a transmitter should fail or a packet being transmitted by the transmitter be faulty, it is important for the receiver to be able to notified of the error so that it can react appropriately to reduce or eliminate the possibility of losing data. Typically, transmitters do not have error recovery mechanisms because their implementation can tend to be complicated. Therefore, the natural response of a faulty transmitter is to reset itself and then wait for instructions from its control unit. The transmitter's sudden failure might cause an unpredictable behavior on the receiver side, which in turn could have a catastrophic impact on the entire data transmission system.